Input circuits have been incorporated into chip technologies for many years to provide fast input buffers which protect deep sub-micron CMOS transistors from overvoltage stress.
Three such prior art input buffer circuits are shown in FIGS. 1A-C. The circuit 1 in FIG. 1A has two field effect transistors (FETs) 100a, 100b. Field effect transistor 100a is an n-type field effect transistor, whereas FET 100b is a p-type field effect transistor. An input pad 110 is connected to the drain terminal of FET 100a. The gate terminal of FET 100a is connected to voltage source V.sub.DD. The source terminal of FET 100a is connected to a voltage restoring circuit 120, in the form of FET 100b having its gate and source terminals coupled through an inverter 130. The drain terminal of FET 100b is connected to a power supply V.sub.DD. Further, two inverters 130 are connected in series and coupled to the source terminal of FET 100b.
A problem with the input circuit of FIG. 1A is that the voltage restoring circuit 120 conflicts with external pull-down resistors (not shown), which slow the speed and effectiveness of the circuit. The voltage restoring circuit 120 "pulls-up" the voltage to a "strong" HIGH logic level when FET 100b is switched ON. The large impedance of the external resistors (not shown) oppose the effectiveness of the voltage restoring circuit 120 to produce this "strong" HIGH logic level.
Another prior art input circuit is shown in FIG. 1B. The circuit 2 of FIG. 1B is composed of an input pad 110 connected to the drain terminal of FET 100a. The gate terminal of FET 100a is connected to a voltage source V.sub.DD. The source terminal of FET 100a is connected to series connected inverters 130a, 130b, and output Y is generated.
This transistor 100a plays an important role in the operations of the circuit 2 of FIG. 1B. For example, if the transistor 100a was not included, then when the input pad 110 is powered up, e.g. to five volts, the gate-to-source voltage on the n-type FET (not shown) of the inverter 130a will be five volts and such n-type FET would pull the output of the inverter 130a to ground. This would cause the p-type FET (not shown) of the inverter 130a to have a gate-to-drain voltage of five volts. For deep submicron architecture neither of these results would be acceptable.
With the inclusion of FET 100a, however, the voltage at node A will never rise above the voltage on the gate terminal of FET 100a less its threshold drop (for DC conditions and long settling times, the threshold may be large). Therefore, the voltage at node A will be less than the internal voltage V.sub.DD. Hence, the voltages across transistor 100a and the n-type and p-type FETs (not shown) of the inverter 130a are maintained in a range to achieve reasonable long-term reliability.
The circuit 2 of FIG. 1B does not have the conflict disadvantage characteristic of circuit 1 of FIG. 1A, however, it has the disadvantage of leaking DC current because the p-channel device (not shown) in inverter 130a is never completely turned off.
A third prior art input circuit is shown in FIG. 1C. The circuit 3 of FIG. 1C is composed of a pad input 110 connected to the drain terminal of FET 100a. The gate terminal of FET 100a is connected to a voltage source V.sub.DD. The source terminal of FET 100a is connected to a CMOS inverter 140. This CMOS inverter 140 is composed of an n-type FET 100c and a p-type FET 100d.
The drain terminal of FET 100d is connected to a diode 120a, which is a p-type FET 100e, having its gate and source terminals coupled together. The drain of FET 100e is connected to a voltage source V.sub.DD.
The output of the CMOS inverter 140 is connected to voltage restoring circuit 120, which is FET 100b having its gate and source terminals coupled through an inverter 130. The drain of FET 100b is connected to a voltage source V.sub.DD. Further, another inverter 130 is coupled to the source terminal of FET 100b.
Although the circuit 3 in FIG. 1C avoids the disadvantages of the circuits shown in FIGS. 1A and 1B, the circuit 3 of FIG. 1C is slow. Furthermore, it also has a natural magnitude hysteresis. This hysteresis will slow down the AC performance, but for any input, the output results will consistently be the same.
Furthermore, to ensure threshold voltages and reasonable speeds, the sizes of p-type FETs 100d and 100e must be made large. The reason for the dimensional differences between the n-type and p-type FETs stems from the characteristic differences between the devices. The relationship between PMOS and NMOS transistors is such that for devices having the same dimensions, the current in a PMOS transistor is less than half of that in an NMOS device and the ON resistance of a p-channel MOSFET is nearly three times that for an n-channel MOSFET.
Both circuits 1 and 3 represented in FIGS. 1A and 1C inherently have a large amount of hysteresis (one-ended hysteresis). To meet the 0.8 volt "low" and two volt "high" thresholds (for 3.3 volt systems), the propagation times from low-to-high and from high-to-low will have a large amount of skew between them.
Alternatively, to achieve the same values of current and ON resistance as in an NMOS transistor, the channel width/length ratio must be increased to account for the lower hole mobility. This results in PMOS devices requiring nearly three times the area of an equivalent NMOS device.
It is thus desirable to provide a fast input buffer which protects deep sub-micron CMOS transistors from overvoltage stress with minimal DC power requirements.
Furthermore, it is desirable to provide a fast input buffer which protects deep sub-micron CMOS transistors from overvoltage stress which has no unusual bus loading and is faster than current I/O circuitry.
It is also desirable to provide a fast input buffer which protects deep sub-micron CMOS transistors from overvoltage stress which meets transistor-transistor logic (TTL) thresholds and has symmetrical response times for fast propagation times from LOW logic level to HIGH logic level (T.sub.PLH) and from HIGH logic level to LOW logic level (T.sub.PHL).